X

FPGA Based Signal Processing Systems

By Prof. P. Sumathi   |   IIT Roorkee
Learners enrolled: 609
ABOUT THE COURSE:

This course introduces Verilog basics and development of Verilog modules for digital systems especially combinational and sequential circuits. This course further focuses on implementation of essential signal processing algorithms, such as Fourier transform, digital filters, Generalized Discrete Signal Processing Networks, and adaptive filters with FPGA. Targeting Xilinx and Altera FPGAs through its integrated design suites will be taught in this course.

INTENDED AUDIENCE: UG (final year), PG and PhD students of Electrical, Electronics, and Instrumentation students.

PREREQUISITES: Basic courses on Digital Circuits and Signal Processing

INDUSTRY SUPPORT: Qualcomm, Texas Instruments, Intel Corporation
Summary
Course Status : Upcoming
Course Type : Elective
Language for course content : English
Duration : 12 weeks
Category :
  • Electrical, Electronics and Communications Engineering
  • VLSI design
Credit Points : 3
Level : Postgraduate
Start Date : 19 Jan 2026
End Date : 10 Apr 2026
Enrollment Ends : 26 Jan 2026
Exam Registration Ends : 13 Feb 2026
Exam Date : 17 Apr 2026 IST
NCrF Level   : 4.5 — 8.0

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.


Page Visits



Course layout

Week 1:  Introduction to FPGA: programmability, challenges, technology review, DSP and Integrated design suites. Verilog: Introduction

Week 2: Verilog: synthesis, modelling digital circuits, writing testbenches.

Week 3: Structural and Data flow modelling of combinational logic Data flow and Behavioural modelling of combinational logic

Week 4: Modelling sequential logic: flip flops, counters, shift registers

Week 5: Modelling sequential logic: Finite state-machines, Mealy and Moore, Synchronous sequential circuits to state diagrams and vice versa

Week 6: Modelling sequential logic: Different styles of FSM Verilog coding, Memory banks. Timing control and Procedural assignments

Week 7: Synthesis of designed combinational and sequential circuits and targeting FPGA.

Week 8: Arithmetic Basics: Number representations, arithmetic operations, MAC, CORDIC, computation of special functions.

Week 9: Digital Filters with FPGA: FIR Filters

Week 10: Digital Filters with FPGA: IIR Filters

Week 11: Fourier Transform Implementation: DFT, FFT, SDFT and its variants, DCT

Week 12: General DSP network, Goertzel Algorithm, and Adaptive filter Implementation.

Books and references

  • Zvi Kohavi and Niraj K. Jha, “Switching and Finite Automata Theory”, third edition, Cambridge University Press, 2006.
  • John F Wakerly, “Digital Design Principles and Practices, Fourth Edition, Pearson Prentice Hall, 2010. 
  • Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, second edition, Tata Mcgraw-Hill, 2007.
  • Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, second edition, Prentice Hall, 2003.
  • Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL”, second edition, Pearson, 2011.
  • Roger Woods, John Mcallister, Gaye Lightbody, Ying Yi, “FPGA-based Implementation of Signal Processing Systems”, second edition, John Wiley & Sons, Ltd., 2017.
  • Uwe Meyer-Baese, “Digital Signal Processing with Field Programmable Gate Arrays”, third edition, Springer, 2007.

Instructor bio

Prof. P. Sumathi

IIT Roorkee
Dr. P. Sumathi is currently Professor in the Department of Electrical Engineering, Indian Institute of Technology Roorkee, Uttarakhand, India. She is associated with IIT Roorkee since 2011. She received B.E in Electrical and Electronics Engineering from S.R.M Engineering College, Chennai, India in 1996, and M.E in Control and Instrumentation from College of Engineering Guindy, Anna University, Chennai, India in 2002. She received her Ph.D. in Electrical Engineering from Indian Institute of Technology Madras, Chennai, India in 2009. Her pedagogical experience spans over 20 years, in teaching undergraduate and post graduate students. She teaches the course on digital signal processing, digital electronic circuits and systems, signals and systems, and FPGA implementation of signal processing systems. Her research interests span over Instrumentation: Sensors, Interfacing Circuits, Capacitance and Sensing, Advanced Driver Assistant Systems, Signal and Image Processing, Sliding DFT, Artificial Intelligence, Control: Phase/Frequency Locking Schemes, Parameter Estimation. She is senior member of IEEE.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: April 17, 2026 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

Please note that assignments encompass all types (including quizzes, programming tasks, and essay submissions) available in the specific week.

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Roorkee .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team
MHRD logo Swayam logo

DOWNLOAD APP

Goto google play store

FOLLOW US