Memory Device Technology for AI/ML Computing

By Prof. Shubhadeep Bhattacharjee | IIT Hyderabad

Learners enrolled: 1644 | Exam registration: 308

ABOUT THE COURSE:

A paradigm shift from logic-oriented, deterministic computing to data-driven, heuristic computing has ushered in the era of AI/ML. This change has been catalyzed by advances in memory and storage technology which has made ‘big data’ accessible for computing. In this course, first, we do a deep dive into (a) the hierarchical memory-storage organization (b) peripherals and subsystem architecture and (c) individual memory devices (SRAM, DRAM, NANDFLASH and e-NVMs) that enable modern day computing. Second, we understand why, despite these advances, current hardware systems are unable to meet the requirements for AI/ML based computing. Finally, we see how these devices can be employed in architectures such as deep and spiking neural networks which will support low-power AI/ML computing.

INTENDED AUDIENCE:

1. 3^rd and 4^th UG (EE and ECE) students interested in Semiconductor devices and VLSI Design, who have finished basic courses in Semiconductor devices and circuits.

2. MTech and PhD students working in Memory Device Technology, Neuromophic devices, Hardware for AI/ML

PREREQUISITES: Introductory UG course in semiconductor devices and Electrical circuits. Knowledge of Analog circuits is desirable but not mandatory.

INDUSTRY SUPPORT:

Micron Inc (Have taken guest lectures for this course), Global Foundries, Intel, TSMC.
MTech Students have given feedback that this course is useful for placements in semiconductor-based companies.

Summary

Course Status :	Ongoing
Course Type :	Elective
Language for course content :	English
Duration :	12 weeks
Category :	Electrical, Electronics and Communications Engineering
Credit Points :	3
Level :	Undergraduate/Postgraduate
Start Date :	19 Jan 2026
End Date :	10 Apr 2026
Enrollment Ends :	02 Feb 2026
Exam Registration Ends :	20 Feb 2026
Exam Date :	17 Apr 2026 IST
NCrF Level	4.5 — 8.0

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

WEEK 1

W1.0: Introductory video

W1.1: Evolving Computing Paradigms

W1.2: Von Neumann Architecture.

W1.3: Memory Hierarchy and Classifications

W1.4: Evolution of memory hierarchy with device technology

W1.5: Classifications within memory hierarchy

WEEK 2

W2.1: Practical Implementation of Memory Hierarchy

W2.2: Global Memory market Part 1

W2.3: Global memory market part 2

W2.4: Memory Array Architecture Part 1

W2.5: Memory Array Architecture Part 2

WEEK 3

W3.1: Analog Memory Peripheral

W3.2: Memory area efficiency and block level design

W3.3: SRAM - introduction and cell structure

W3.4: SRAM-Memory effect and HOLD operation

W3.5: SRAM-Read operation

W3.6: SRAM Read Operation Timing Diagram

WEEK 4

W4.1: SRAM Write operation

W4.2: Noise margins

W4.3: SRAM - Biasing, 8T SRAM and Scaling

W4.4: DRAM Introduction and Memory Wall

W4.5: DRAM Sub-system Architecture

WEEK 5

W5.1: 1T-1R DRAM Cell and leakage paths of a storage node

W5.2: DRAM Refresh and Charge Sharing

W5.3: DRAM Read Write Timing Diagrams

W5.4: DRAM Scaling Challenges and Solutions

W5.5: Intro to NAND Flash and Flash cell part-1

WEEK 6

W6.1: NAND Flash cell - Floating gate vs charge trap

W6.2: Types of Flash Organisation , NAND Organisation

W6.3: NAND Flash Program Operation

W6.4: NAND Erase and Read Operations

W6.5: Advancements in NAND Flash technology and ISPP

WEEK 7

W7.1: NAND Flash Reliability challenges, 3-D NAND

W7.2: Review of Part-1 (Mod1-5)

W7.3: eNVMs Fundamentals of two-terminal Memristors

W7.4: eNVMs PCRAMs Fundamentals of Phase Change Memories

W7.5: eNVMs PCRAMs Technology and commercialization

WEEK 8

W8.1: eNVMs RRAMs Fundamentals

W8.2: eNVMs RRAMs VCRAM and CBRAM

W8.3: eNVMs RRAMs - Performance Metrics & Commercialization

W8.4: eNVMs MRAM spin GMR TMR

W8.5: eNVM MRAMs Field and STT MRAM

WEEK 9

W9.1: eNVM MRAM SOT and Commercialization

W9.2: Classification and development of AIML paradigm

W9.3: AIML task and introduction to artificial neuron

W9.4: Scaling up artificial neuron to ANN

W9.5: ANNs backprop, inference and different architectures of neural networks

WEEK 10

W10.1: Convolution operations

W10.2: Convolution neural networks

W10.3: Computational and energy cost of AIML

W10.4: Introduction to Neuromorphic Computing

W10.5: Structure and Behaviour of the LIF Neuron

WEEK 11

W11.1: HW Implementation of LIF Neuron

W11.2: Synaptic Plasticity and STDP

W11.3: HW Implementation of Synaptic Plasticity

W11.4: Intro to SNNs and Spike encoding

WEEK 12

W12.1: Supervised and Unsupervised Learning in SNNs

W12.2: HW implementation of SNNs

W12.3: Intro to In Memory Computing (IMC)

W12.4: HW implementations of IMC

W12.5: Conclusion and Future Trends

Books and references

1. Yu S. Semiconductor Memory Devices and Circuits. CRC Press; 2022 Apr 19.

2. Wan, Q., & Shi, Y. (Eds.). (2022). Neuromorphic Devices for Brain-inspired Computing: Artificial

Intelligence, Perception, and Robotics. John Wiley & Sons.

3. References and review articles given in lecture slides

Instructor bio

Prof. Shubhadeep Bhattacharjee

IIT Hyderabad

Prof. Shubhadeep B has been working as an Assistant Professor at Electrical Engineering, Indian Institute of Technology, Hyderabad since Dec 2021. He graduated from BITS Pilani [B.E. (Hons.), EEE] in 2011 followed by a 3-year industrial position at ST Microelectronics in the design of FDSOI technology-based SoCs (2011-14). Shubhadeep was a Visvesvaraya Ph.D. fellow at CeNSE, IISc Bangalore (2014-18) where he worked on sub-thermionic 2D transistors and was awarded the Institute gold medal for best Ph.D. thesis. Post Ph.D., he worked as a research scientist (post doc) with Intel labs at Tyndall National Institute to explore neuromorphic devices on 2D materials [2018-19]. Next, he moved to the University of Manchester to explore emergent quantum devices based on 2D moire superlattices [2019-21]. His research interests are in the development of electronic devices for the next generation of low-power computing.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.

The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).

Date and Time of Exams: April 17, 2026 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.

Registration url: Announcements will be made when the registration form is open for registrations.

The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.

Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

Please note that assignments encompass all types (including quizzes, programming tasks, and essay submissions) available in the specific week.

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Hyderabad .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team