Low Voltage CMOS Circuit Operation

By Prof. Anand Bulusu | IIT Roorkee

Learners enrolled: 2093 | Exam registration: 144

ABOUT THE COURSE:This course would deal with the circuit design techniques in low voltage regime, where the PVT variations are malfunctioning the circuit performance. The understanding of MOSFET or/and FinFET operation in weak inversion region, followed by development of robust circuit designing techniques in Digital, Analog and Mixed-signal designs.
Objective: To understand essential aspects of low voltage operation of MOSFETs and CMOS circuits comprehensively and to learn to design such circuits.

INTENDED AUDIENCE: Student interested in VLSI circuit design and device-circuit interaction.

PREREQUISITES: Courses on digital logic design, digital VLSI and analog circuit design and basic MOS device physicsax

INDUSTRY SUPPORT: All VLSI Design companies
(Cadence, Synopsys, Mentor Graphics, Texas Instruments, Micron etc.). Already, industry professionals who are students of IITR’s M.Tech (VLSI) program take this course as an elective.

Summary

Course Status :	Ongoing
Course Type :	Elective
Duration :	8 weeks
Category :	Electrical, Electronics and Communications Engineering VLSI design
Credit Points :	2
Level :	Undergraduate/Postgraduate
Start Date :	22 Jul 2024
End Date :	13 Sep 2024
Enrollment Ends :	05 Aug 2024
Exam Registration Ends :	16 Aug 2024
Exam Date :	21 Sep 2024 IST

Note: This exam date is subjected to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week 1:

Lecture 1 : Introduction and Motivation

Module 1 : MOSFET operation in weak and moderate inversion regions:

Lecture 2 : Review of MOSFET operation

Lecture 3 : Review of MOSFET operation

Lecture 4 : Basic charge model

Lecture 5 : Basic charge model

Week 2:

Lecture 6 : Basic charge model

Lecture 7 : Basic charge model

Lecture 8 : Basic charge model

Module 2 : FINFET operation in weak and moderate inversion regions:

Lecture 9 : Review of FinFET operation

Lecture 10 : Review of FinFET operation

Week 3:

Lecture 11 : Basic charge model

Lecture 12 : Basic charge model

Lecture 13 : Basic charge model

Module 3 : MEP for low voltage operation and Transistor sizing for Near Threshold circuits:

Lecture 14 : Minimum Energy Point (MEP)

Lecture 15 : Transistor sizing for combinational circuits (Inverter)

Week 4:

Lecture 16 : Transistor sizing for combinational circuits (Inverter)

Lecture 17 : Transistor sizing for combinational circuits (Stacked gates)

Lecture 18 : Transistor sizing for combinational circuits (Stacked gates)

Lecture 19 : Transistor sizing for combinational circuits (Stacked gates)

Lecture 20 : Multi-stage circuit sizing

Week 5:

Lecture 21 : Multi-stage circuit sizing

Lecture 22 : Effective drive current models for NTV operation

Lecture 23 : Effective drive current models for NTV operation

Module 4 : Sequential Circuits for Near-Threshold Voltage operations:

Lecture 24 : Operation of sequential cells: Latch and Flipflop

Lecture 25 : Operation of sequential cells: Latch and Flipflop

Week 6:

Lecture 26 : Warning Flip-Flop design and operation

Lecture 27 : Warning Flip-Flop design and operation

Lecture 28 : Warning Flip-Flop design and operation

Lecture 29 : PVT variation analysis in NTV circuits

Lecture 30 : PVT variation analysis in NTV circuits

Week 7:

Module 5 : Near-Threshold Voltage digital CMOS memory design:

Lecture 31 : Introduction, Types of memory (SRAM/DRAM/NVM/ROM)

Lecture 32 : SRAM read/write operation

Lecture 33 : SRAM 6T bit cell design (CR/PR)

Lecture 34 : SRAM 6T bit cell design (CR/PR)

Lecture 35 : Noise Margin (HSNM/RSNM/WSNM)

Week 8:

Lecture 36 : Memory peripherals (Sense Amplifier & Pre-charge)

Lecture 37 : Memory peripherals (Decoder/ Column-Mux/Drivers)

Module 6 : Near-Threshold Voltage based special circuits:

Lecture 38 : Resilient circuits

Lecture 39 : Level shifters

Lecture 40 : Level shifters

Books and references

1. Low voltage CMOS VLSI Circuits, by J. B. Kuo and J.H Lou, Wiley 1999.
2. Sub-Threshold Design for Ultra Low-Power Systems, A. Wang, B. H.Calhoun, and A.P. Chandrakashan, Springer 2006.
3. Charge-based MOS transistor Modelling The EKV Model for Low-Power and RF IC Design By C.C. Enz and E.A. Vittoz, Wiley 2006.
4. Digital Integrated Circuits, A Design Prospective by J.M. Rabaey, Prentice Hall 2002
5. CMOS Mixed Signal Circuit Design by R.J. Baker, Wiley 2003.
6. Analog Integrated Circuit Design by Tony Chan Carusone, David A. Johns and Kenneth W. Martin, Wiley 2011.

Instructor bio

Prof. Anand Bulusu

IIT Roorkee

Prof.Anand Bulusu received the Ph.D. degree from IIT Bombay, Mumbai, India, in 2006. He worked as a Senior Research Engineer from 2007-08 in Silicon Technology Solutions groups of Freescale Semiconductor (present NXP Semiconductor). Since December 2008, he has been working as a faculty member in the Electronics and Communication Engineering Department of Indian Institute of Technology (IIT) Roorkee, Roorkee, India, where he is currently a professor. His current research interests include circuit performance models and design, devicecircuit interaction, and digital/analog/mixed-signal circuit design. The emphasis of his group’s work is in understanding device-circuit interaction and developing circuit design methodologies. His group has published several papers in reputed journals, presented in reputed conferences and also works on industry-linked projects in these areas.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: 21 September 2024 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 6 assignments out of the total 8 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Roorkee .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team

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