Course Status : | Completed |
Course Type : | Elective |
Duration : | 12 weeks |
Category : |
|
Credit Points : | 3 |
Level : | Undergraduate/Postgraduate |
Start Date : | 22 Jan 2024 |
End Date : | 12 Apr 2024 |
Enrollment Ends : | 05 Feb 2024 |
Exam Registration Ends : | 16 Feb 2024 |
Exam Date : | 21 Apr 2024 IST |
Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.
Week-1: Introduction to VLSI Physical Design
Lec-1: Introduction to VLSI Design
Lec-2: VLSI Physical Design
Lec-3: Complexity Analysis for Algorithms
Lec-4: Graphs for Physical Design
Lec-5: Graph searching Algorithms
Lec-6: Spanning Tree and Shortest Path Algorithms
Week-2: Static Timing
Analysis (STA) – 1
Lec-7: Overview
of Timing Analysis
Lec-8: Timing
Arcs and Unateness
Lec-9: Delay
Parameters of Combinational Circuits
Lec-10: Delay
Parameters of Sequential Circuit
Lec-11: Timing
Analysis in Sequential Circuit
Lec-12: STA in
Sequential Circuit with Clock Skew – Part 1
Week-3: Static Timing
Analysis (STA) – 2
Lec-13: STA in
Sequential Circuit with Clock Skew – Part 2
Lec-14: STA in
Sequential Circuit with Clock Jitter
Lec-15: STA
considering OCV and CRPR ( Setup check)
Lec-16: STA
considering OCV and CRPR ( Hold check)
Lec-17: STA for Combinational Circuits – Part 1
Lec-18: STA for Combinational Circuits – Part 2
Week-4: Partitioning
Lec-19: Introduction
to Partitioning – Part 1
Lec-20: Introduction
to Partitioning – Part 2
Lec-21: Partitioning
Algorithms
Lec-22: Kernighan
– Lin (KL) Algorithm
Lec-23: Fidduccia-Mattheyeses(FM)
Algorithm
Week-5: Chip Planning
Lec-24: Introduction
to Floorplanning
Lec-25: Floorplanning
Representations
Lec-26: Floorplanning
Algorithms – Part 1
Lec-27: Floorplanning Algorithms – Part 2
Lec-28: Pin
Assignment and Power - Ground Routing
Week-6: Placement
Lec-29: Introduction
to Placement
Lec-30: Wirelength
estimation techniques
Lec-31: Min-cut
placement
Lec-32: Placement
Algorithms
Lec-33: Placement
algorithms and legalization
Week-7: Clock Routing
Lec-34: Introduction
to Clock Tree Synthesis
Lec-35: Clock
Routing Algorithms – Part 1
Lec-36: Clock
Routing Algorithms – Part 2
Lec-37: Clock
Routing Algorithms – Part 3
Week-8: Global Routing
Lec-38: Introduction
and Optimization Goals
Lec-39: Single net routing (Rectilinear routing)
Lec-40: Global Routing in the connectivity graph
Lec-41: Finding
Shortest Paths with Dijkstra’s Algorithm
Lec-42: Full-Netlist
Routing
Week-9: Detailed Routing
Lec-43: Introduction:
Detailed Routing
Lec-44: Channel
Routing Algorithms – Part 1
Lec-45: Channel
Routing Algorithms – Part 2
Lec-46: Switchbox
and Over the cell routing
Week-10: Advanced
Concepts of Timing Analysis
Lec-47: Timing
analysis in latches
Lec-48: Time borrowing in latches
Lec-49: Crosstalk Analysis
Lec-50: SSTA - Statistical Static Timing Analysis
Week-11: Input
files for VLSI physical design flow
Lec-51: Standard
Cell Library
Lec-52: Low Power Cells in Standard Cell Library
Lec-53: Sub-threshold
Standard Cell Library
Lec-54: Timing Library for Standard cells
Lec-55: PDK and
Other files
Week-12: Open-source VLSI
Physical Design flow
Lec-56: Open-Source tool installation and Qflow
Lec-57: Open-Source tool- YOSYS
Lec-58: OpenSTA Static Timing Analyzer
Lec-59: OpenROAD Physical Synthesis Flow – Part 1
Lec-60: OpenROAD
Physical Synthesis Flow – Part 2
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