VLSI Physical Design with Timing Analysis

By Prof. Bishnu Prasad Das   |   IIT Roorkee
Learners enrolled: 6673   |  Exam registration: 949
The course covers all the steps of VLSI Physical design flow needed for VLSI chip design. It includes all the steps of VLSI Physical design such as partitioning, chip planning, placement, Routing, and finally Clock routing. As the timing of digital circuits is important, three weeks will be completely dedicated to Static Timing Analysis (STA). A demo of several Open-source tools such as Qflow, Yosys, OpenSTA, and OpenROAD is also included in the course.

INTENDED AUDIENCE: It is a course for UG, PG and PhD students. BTech (ECE), BTech (CSE), BTech (EE), and BTech (Any other branch) who has completed a Basic Digital Electronics course. 

MTech (Micro-electronics and VLSI), MTech (VLSI) and related fields, MTech (ECE), Ph.D. (ECE), and Ph.D. (CSE) students

PREREQUISITES: The digital design course is a pre-requisite for this course.

INDUSTRY SUPPORT: All VLSI industries, For example: Intel, AMD, TI, Qualcomm, Analog Devices, ST-micro-electronics and many more.
Course Status : Completed
Course Type : Elective
Duration : 12 weeks
Category :
  • Electrical, Electronics and Communications Engineering
  • VLSI design
Credit Points : 3
Level : Undergraduate/Postgraduate
Start Date : 22 Jan 2024
End Date : 12 Apr 2024
Enrollment Ends : 05 Feb 2024
Exam Registration Ends : 16 Feb 2024
Exam Date : 21 Apr 2024 IST

Note: This exam date is subjected to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week-1:  Introduction to VLSI Physical Design

Lec-1: Introduction to VLSI Design

Lec-2: VLSI Physical Design

Lec-3: Complexity Analysis for Algorithms

Lec-4: Graphs for Physical Design

Lec-5: Graph searching Algorithms

Lec-6: Spanning Tree and Shortest Path Algorithms

Week-2: Static Timing Analysis (STA) – 1

Lec-7: Overview of Timing Analysis

Lec-8: Timing Arcs and Unateness

Lec-9: Delay Parameters of Combinational Circuits

Lec-10: Delay Parameters of Sequential Circuit

Lec-11: Timing Analysis in Sequential Circuit

Lec-12: STA in Sequential Circuit with Clock Skew – Part 1

Week-3: Static Timing Analysis (STA) – 2

Lec-13: STA in Sequential Circuit with Clock Skew – Part 2

Lec-14: STA in Sequential Circuit with Clock Jitter

Lec-15: STA considering OCV and CRPR ( Setup check)

Lec-16: STA considering OCV and CRPR ( Hold check)

Lec-17: STA for Combinational Circuits – Part 1

Lec-18: STA for Combinational Circuits – Part 2

Week-4: Partitioning

Lec-19: Introduction to Partitioning – Part 1

Lec-20: Introduction to Partitioning – Part 2

Lec-21: Partitioning Algorithms

Lec-22: Kernighan – Lin (KL) Algorithm

Lec-23: Fidduccia-Mattheyeses(FM) Algorithm

Week-5: Chip Planning

Lec-24: Introduction to Floorplanning

Lec-25: Floorplanning Representations

Lec-26: Floorplanning Algorithms – Part 1

Lec-27: Floorplanning Algorithms – Part 2

Lec-28: Pin Assignment and Power - Ground Routing

Week-6: Placement

Lec-29: Introduction to Placement

Lec-30: Wirelength estimation techniques

Lec-31: Min-cut placement

Lec-32: Placement Algorithms

Lec-33: Placement algorithms and legalization

Week-7: Clock Routing

Lec-34: Introduction to Clock Tree Synthesis

Lec-35: Clock Routing Algorithms – Part 1

Lec-36: Clock Routing Algorithms – Part 2

Lec-37: Clock Routing Algorithms – Part 3

Week-8: Global Routing

Lec-38: Introduction and Optimization Goals

Lec-39: Single net routing (Rectilinear routing)

Lec-40: Global Routing in the connectivity graph

Lec-41: Finding Shortest Paths with Dijkstra’s Algorithm

Lec-42: Full-Netlist Routing

Week-9: Detailed Routing

Lec-43: Introduction: Detailed Routing

Lec-44: Channel Routing Algorithms – Part 1

Lec-45: Channel Routing Algorithms – Part 2

Lec-46: Switchbox and Over the cell routing

Week-10: Advanced Concepts of Timing Analysis

Lec-47: Timing analysis in latches

Lec-48: Time borrowing in latches

Lec-49: Crosstalk Analysis

Lec-50: SSTA - Statistical Static Timing Analysis

Week-11: Input files for VLSI physical design flow

Lec-51: Standard Cell Library

Lec-52: Low Power Cells in Standard Cell Library

Lec-53: Sub-threshold Standard Cell Library

Lec-54: Timing Library for Standard cells

Lec-55: PDK and Other files

Week-12: Open-source VLSI Physical Design flow

Lec-56: Open-Source tool installation and Qflow

Lec-57: Open-Source tool- YOSYS

Lec-58: OpenSTA Static Timing Analyzer

Lec-59: OpenROAD Physical Synthesis Flow – Part 1

Lec-60: OpenROAD Physical Synthesis Flow – Part 2

Books and references

1. Kahng, A.B., Lienig, J., Markov, I.L., Hu, J., “VLSI Physical Design: From Graph Partitioning to Timing Closure”, Springer.
2. Sherwani, N.A., “Algorithm for VLSI Physical Design Automation”, 2nd Ed., Kluwer.
3. J. Bhasker and Rakesh Chadha, “Static Timing Analysis for Nanometer Designs A Practical Approach” Springer 2009
4. Bhatnagar, H. “Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and Prime Time”; Kluwer Academic Publishers: New York, NY, USA, 2002

Instructor bio

Prof. Bishnu Prasad Das

IIT Roorkee
Prof. Bishnu Prasad Das is currently an Associate Professor in the Department of Electronics and Communication Engineering, IIT, Roorkee. He obtained his Ph.D. degree in Electronics Design and Technology from Indian Institute of Science (IISc), Bangalore, India, in 2009.

During May 2019 to July 2019, he worked as a Visiting Fellow at Tokyo Institute of Technology, Tokyo, Japan. From 2012 to 2013, he worked as a Post-Doctoral Researcher with the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA. From 2009 to 2012, he worked as a Post-Doctoral Researcher with Kyoto University, Kyoto, Japan. He is currently an Associate Professor with the Department of Electronics and Communication Engineering, IIT Roorkee, India. His current research interests include in-memory computation architectures, hardware security, reduced instruction set computer (RISC)-V processor architecture, wearable healthcare devices, and ultralow-power circuit design.

Prof. Das was a recipient of the Young Faculty Research Fellowship from the Ministry of Electronics and Information Technology (MeitY), Government of India, in 2018. He was awarded the Faculty Fellow from Divyasampark iHUB Roorkee, India, in 2021.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: 21 April 2024 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.


Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Roorkee .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team

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