Digital System Design

By Prof. Neeraj Goel | IIT Ropar

Learners enrolled: 6867 | Exam registration: 1620

ABOUT THE COURSE:

Digital system design course focuses on design digital system from scratch. The course focuses on designing combinational and sequential building blocks, using these building blocks to design bigger digital systems. During this course we also learn how to use Verilog to design/model a digital system.

INTENDED AUDIENCE : CSE, EE, ECE undergraduate students

PREREQUISITES : None

INDUSTRIES SUPPORT : Any VLSI related company: Intel, AMD, TI, nVIDIA, Qualcomm, etc.

Summary

Course Status :	Completed
Course Type :	Core
Language for course content :	English
Duration :	12 weeks
Category :	Electrical, Electronics and Communications Engineering
Credit Points :	3
Level :	Undergraduate
Start Date :	22 Jan 2024
End Date :	12 Apr 2024
Enrollment Ends :	05 Feb 2024
Exam Registration Ends :	16 Feb 2024
Exam Date :	20 Apr 2024 IST

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week 1: Introduction of digital systems. Number system

Week 2: Number representation: BCD, floating point numbers

Week 3: Boolean algebra, application of Boolean algebra in minimization of Boolean expressions

Week 4: Boolean minimization using K-map and Quine McCluskey method. Introduction to Verilog

Week 5: MSI Logic: Multiplexer, encoder, decoder

Week 6: Arthimetic circuits: Adder, subtractor, multiplier, comparator

Week 7: Latches and flipflop (SR, JK, T, D), counters

Week 8: Sequential logic like Registers, introduction to behavior modeling in Verilog

Week 9: Finite state machine, state graphs and tables.

Week 10: Reduction of state table and state assignments. Arithmetic circuits using sequential design.

Week 11: Register transfer level (RTL) design, RTL design examples

Week 12: FPGA, VLSI design flow using HDL, introduction to behavior, logic and physical synthesis.

Books and references

1. Digital Design: with an introduction to Verilog HDL by M. Morris Mano and Mechael D. Ciletti, 5th Edition, Pearson Education, 2013.

2. Advanced Digital Design with the Verilog HDL by Michael D Ciletti, 2nd edition, Pearson education, 2017.

3. Fundamentals of Logic Design by Roth and Kinney. 7th edition, Cengage learning, 2014

4. Digital system design using verilog by Roth, John and Lee, 1st edition, Cengage learning, 2016.

Instructor bio

Prof. Neeraj Goel

IIT Ropar

Dr. Neeraj Goel is an Assistant Professor in the Department of Computer Science and Engineering at IIT Ropar. His research interest includes processor architecture, SoC design, SoC modeling and low power design. He received B.Tech degree in Electronics and communication from NIT Kurukshetra, M.Tech degree in VLSI Design Tools and Technology from IIT Delhi and PhD in Computer Science and Engineering from IIT Delhi.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: 20 April 2024 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Madras .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team

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