Phase-locked loops

By Prof. Saurabh Saxena | IIT Madras

Learners enrolled: 1097

ABOUT THE COURSE:
This course will emphasize on developing intuition behind frequency synthesizer design, learning mathematical basis behind operation, and realizing PLLs at architecture and circuit level. The students will be exposed to state-of-the-art frequency synthesis techniques used in analog/digital integer-N PLLs.

This course will equip students with skills to analyze, debug, and evaluate a PLL design at analytical and transistor levels both. The students will be able to use their knowledge and skills while generating a clock signal in a power-efficient manner for requirements of a synchronous system.

PRE-REQUISITES: EE3002 (http://www.ee.iitm.ac.in/vlsi/courses/ee3002_2017/start)

INTENDED AUDIENCE: B.Tech (6th semester onwards), M.Tech./M.S./Ph.D. (1st semester onwards)

INDUSTRY SUPPORT: Texas Instruments, Intel, Qualcomm, Samsung, Cadence

Summary

Course Status :	Completed
Course Type :	Elective
Language for course content :
Duration :	12 weeks
Category :	Electrical, Electronics and Communications Engineering
Credit Points :	3
Level :	Undergraduate/Postgraduate
Start Date :	25 Jul 2022
End Date :	14 Oct 2022
Enrollment Ends :	08 Aug 2022
Exam Date :	29 Oct 2022 IST

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week 1: Basic concepts in PLL, Type-I PLL

Week 2: Frequency acquisition in PLLs

Week 3: Phase/frequency error detectors, Charge-pump based type-II PLLs

Week 4: Noise analysis in charge-pump PLLs

Week 5: Design of PLL building blocks: PFD

Week 6: Design of PLL building blocks: Charge-pump

Week 7: Design of PLL building blocks: Ring oscillators

Week 8: Design of PLL building blocks: Supply regulated oscillators

Week 9: Design of PLL building blocks: Loop filter

Week 10: Split-tuned Analog PLL

Week 11: Digital PLLs

Week 12: Noise analysis in digital PLLs

Books and references

F. Gardner, Phaselock Techniques, John Wiley & Sons, 2005.
W. Egan, Phase-Lock Basics, John Wiley & Sons, 2008.
R. Best, Phase-Locked Loops : Design, Simulation, and Applications, McGraw Hill, 2003.

Instructor bio

Prof. Saurabh Saxena

IIT Madras

Prof. Saurabh Saxena (S’10–M’16) received the B.Tech. degree in electrical engineering, the M.Tech. degree in microelectronics and VLSI design from the Indian Institute of Technology Madras, Chennai, India, in 2009, and the Ph.D. degree in electrical and computer engineering from the University of Illinois, Urbana-Champaign, IL in 2015. He is currently an Assistant Professor in the Department of Electrical Engineering at Indian Institute of Technology Madras, Chennai, India.Prof. Saxena is a recipient of Young Faculty Research Fellowship of Visvesvaraya PhD programme of MeitY, GoI. He serves as a reviewer for the IEEE Journal of Solid-StateCircuits, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Very Large Scale Integration Systems, and IEEE International Symposium on Circuits and Systems. His research interests include delta-sigma modulators, high speed I/O interfaces, and clocking circuits.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.

The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).

Date and Time of Exams: 29 October 2022 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.

Registration url: Announcements will be made when the registration form is open for registrations.

The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.

Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.

Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Madras. It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team