C-Based VLSI Design

By Prof. Chandan Karfa | IIT Guwahati

Learners enrolled: 3861

ABOUT THE COURSE :
This course discussed how a C code can be automatically translated into register transfer level (RTL) design using high-level synthesis (HLS). HLS is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. This course will help the student to:
(i) understand the overall HLS flow,
(ii) how a C-code will be converted to its equivalent hardware,
(iii) how to write c-code for efficient hardware generation and
(iv) how the common software compiler optimization can help to improve the circuit performance.
Also, advanced topics like HLS for FPGA targets, HLS for Security, optimizations at RTL level and verification challenges of HLS will be covered. This course will help the student to take up research in the domain of HLS. Also, this course will help the student to become proficient for EDA industries.

INTENDED AUDIENCE : Final year BTech Student, MTech and PhD students, engineers from VLSI industries

PREREQUISITES :

Basic knowledge of digital design
Basic knowledge of Data structures and algorithms
Basic knowledge of Verilog. The students may go through the first six lectures of https://nptel.ac.in/courses/106/105/106105083/ to learn Verilog.

INDUSTRY SUPPORT : Synopsys, Cadence, Mentor Graphics, Intel, Xilinx

Summary

Course Status :	Ongoing
Course Type :	Elective
Duration :	12 weeks
Start Date :	25 Jul 2022
End Date :	14 Oct 2022
Exam Date :	29 Oct 2022 IST
Enrollment Ends :	08 Aug 2022
Category :	Computer Science and Engineering Systems
Credit Points :	3
Level :	Undergraduate/Postgraduate

Page Visits

Course layout

Week-1: Introduction to Electronic Design Automation
Week-2: Introduction to C-based VLSI Design: Background

Week-3: Introduction to C-based VLSI Design: HLS Flow
Week-4: C-Based VLSI Design: Scheduling

Week-5: C-Based VLSI Design: Resource allocation and Binding, Data-path and Controller Generation

Week-6: Efficient Synthesis of C Code
Week-7: Hardware Efficient C Coding
Week-8: Impact of Compiler Optimizations in Hardware

Week-9: Verification of High-level Synthesis

Week-10: FPGA Technology Mapping

Week-11: Securing Design with High-level Synthesis

Week-12: Recent Advances in C-Based VLSI Design

Books and references

1. D. D. Gajski, N. D. Dutt, A.C.-H. Wu and S.Y.-L. Lin, High-Level Synthesis: Introduction to Chip and System Design, Springer, 1st edition, 1992

2. G. De Micheli. Synthesis and optimization of digital circuits, McGraw Hill, India Edition, 2003.

3. Mike Fingeroff, High-Level Synthesis Blue Book, Mentor Graphics Corporation, 2010.

4. Philippe Coussy and Adam Morawiec, High-level Synthesis from Algorithm to Digital Circuit, Springer, 2008

5. David. C. Ku and G. De Micheli, High-level Syntehsis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.

Instructor bio

Prof. Chandan Karfa

IIT Guwahati

Dr. Chandan Karfa is an Assistant Professor in the Dept. of CSE, IIT Guwahati since 2016. He has over fifteen years of teaching and research experience. He has so far taught many courses in UG and PG level in IIT Guwahati. He has worked for five years as Senior R&D engineer in EDA Industry in the domain of High-level Synthesis and Logic Synthesis. He has worked as visiting researcher at New York University, May - July 2019. His research interests include High-level Synthesis, CAD for VLSI, Hardware Security and Formal Verification. He has published more than thirty five research papers in reputed international journals and conferences. He has graduated one PhD student and guided twelve MTech and twenty two BTech projects. He is an IEEE Senior member. He was recently awarded the Qualcomm Faculty Award 2021 which recognizes distinguished faculty research that inspires students and sparks new approaches in key technology areas.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: 29 October 2022 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100

Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75. If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Guwahati .It will be e-verifiable at nptel.ac.in/noc.

Only the e-certificate will be made available. Hard copies will not be dispatched.

Once again, thanks for your interest in our online courses and certification. Happy learning.

- NPTEL team

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