Multi-Core Computer Architecture – Storage and Interconnects

Dr. John Jose is an Assistant Professor in the Department of Computer Science & Engineering, Indian Institute of Technology, Guwahati, Assam since 2015. He completed his Ph.D degree in Department of Computer Science & Engineering, Indian Institute of Technology Madras in the field of computer architecture. He did his B.Tech degree from College of Engineering Adoor, Cochin University, Kerala. He was a rank holder in M.Tech degree from the Vellore Institute of Technology. He had guided over 8 M.Tech thesis and is currently supervising 7 Ph.D thesis and 2 M.Tech thesis. His area of interests is in on-chip interconnection networks, cache management techniques for multicore architectures, non-volatile memory techniques, disaggregated memory systems, fault tolerant and secure NoC designs for large multicore systems. He is the Principal Investigator for SERB-ECRA and MHRD-SPARC projects. He is having active research collaboration with the University of Catania-Italy, University of Essex, UK, University of Florida, USA, and Federal University Naples, Italy. During his doctoral studies in CSE department, IIT Madras he has received the outstanding teaching assistant award for eight consecutive semesters. He is a reviewer for many national and international peer-reviewed journals and members of technical program committee for many IEEE/ACM national and international conferences. He has given many technical presentations in various international conferences held at Brazil, UAE, Singapore, France, Italy, South Korea and USA in the fields of computer design, interconnection networks, and design automation. He has many international IEEE & ACM conference publications and few ACM & IEEE transactions journal papers to his credit. He is the recipient of ACM-SIGDA, IEEE-CEDA, IARCS and DRDO research grants for research presentations held in various international venues. He is the IIT Guwahati coordinator for Ishan Vikas program and Vigyan Jyoti program of MHRD, Govt. of India and course coordinator for MHRD sponsored GIAN course in on-chip interconnects. He has offered two NPTEL Online Certification courses in the area of Computer Architecture. He is a resource person to computer architecture related symposia, workshops and short term courses in many technical institutes all over India. He is a resource person for many career guidance seminars/ teaching pedagogy workshops to various technical institutes and schools. He is a motivational speaker for many companies, school , and higher education institutions. He is an active member of professional societies like ACM, IEEE, ISTE and CSI.