Digital VLSI Testing

By Prof. Santanu Chattopadhyay | IIT Kharagpur

Learners enrolled: 5088

Testing is an integral part of the VLSI design cycle. With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging. Testing occupies 60-80% time of the design process. A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing. Design for testability (DFT) is a matured domain now, and thus needs to be followed by all the VLSI designers. In this context, the course attempts to expose the students and practitioners to the most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in large quantity.

INTENDED AUDIENCE : Any interested learners

PREREQUISITES : Digital Design / Digital Logic

INDUSTRY SUPPORT : Companies involved in development of VLSI chips

Summary

Course Status :	Completed
Course Type :	Core
Language for course content :	English
Duration :	12 weeks
Category :	Electrical, Electronics and Communications Engineering
Credit Points :	3
Level :	Undergraduate/Postgraduate
Start Date :	14 Sep 2020
End Date :	04 Dec 2020
Enrollment Ends :	25 Sep 2020
Exam Date :	19 Dec 2020 IST

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week 1:Introduction: Importance, Challenges, Levels of abstraction, Fault Models, Advanced issues

Week 2:Design for Testability: Introduction, Testability Analysis, DFT Basics, Scan cell design, Scan Architecture

Week 3:Design for Testability: Scan design rules, Scan design flow . Fault Simulation: Introduction, Simulation models

Week 4:Fault Simulation: Logic simulation, Fault simulation

Week 5:Test Generation: Introduction, Exhaustive testing, Boolean difference, Basic ATPG algorithms

Week 6:Test Generation: ATPG for non stuck-at faults, Other issues in test generation Built-In-Self-Test: Introduction, BIST design rules

Week 7:Built-In-Self-Test: Test pattern generation, Output response analysis, Logic BIST architectures

Week 8:Test Compression: Introduction, Stimulus compression

Week 9:Test Compression: Stimulus compression, Response compression

Week 10:Memory Testing: Introduction, RAM fault models, RAM test generation

Week 11:Memory Testing: Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG

Week 12:Power and Thermal Aware Test: Low power BIST, Thermal aware techniques

Books and references

• The exam is optional for a fee. Exams will be on 23 April 2017.

• Time: Shift 1: 9am-12 noon; Shift 2: 2pm-5pm

• Any one shift can be chosen to write the exam for a course.

• Registration url: Announcements will be made when the registration form is open for registrations.

• The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.

Instructor bio

Prof. Santanu Chattopadhyay

IIT Kharagpur

Santanu Chattopadhyay received his BE degree in Computer Science and Technology from Calcutta University (B.E. College) in 1990. He received M.Tech in Computer and Information Technology and PhD in Computer Science and Engineering from Indian Institute of Technology Kharagpur in 1992 and 1996, respectively. He is currently a Professor in the Department of Electronics and Electrical Communication Engineering, IIT Kharagpur. Prior to this, he had been a faculty member in the IIEST Sibpur and IIT Guwahati in the departments of Computer Science and Engineering. In both these places he has taught the subject of Compiler Design several times. His research interests include Digital Design, Embedded Systems, System-on-Chip (SoC) and Network-on-Chip (NoC) Design and Test, Power- and Thermal-aware Testing of VLSI Circuits and Systems. He has published more than 150 papers in reputed international journals and conferences. He has published several text and reference books on Compiler Design, Embedded Systems and other related areas. He is a senior member of the IEEE and an Associate Editor of IET Circuits Devices and Systems journal.

Course certificate

• The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.

• The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).

• Date and Time of Exams: 19 December 2020, Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.

• Registration url: Announcements will be made when the registration form is open for registrations.

• The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.

• Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE:

• Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.

• Exam score = 75% of the proctored certification exam score out of 100

• Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75.

• If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.

• Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Kharagpur. It will be e-verifiable at nptel.ac.in/noc

• Only the e-certificate will be made available. Hard copies will not be dispatched.