Mapping Signal Processing Algorithms to Architectures

By Prof.Nitin Chandrachoodan | IIT Madras

Learners enrolled: 867

Digital Signal Processing typically involves repetitive computations being performed on streams of input data, subject to constraints such as sampling rate or desired throughput. Often such systems need to be implemented under tight constraints on factors such as timing, resources, power or cost. When they are used in embedded systems, it is often worth the effort to design custom architectures that have much better cost tradeoffs than general purpose computing architectures. This course deals with the analysis of such algorithms, and mapping them to architectures that are either custom designed or have specific extensions that make them better suited to certain kinds of operations. Topics covered include fundamental bounds on performance, mapping to dedicated and custom resource shared architectures, and techniques for automating the process of scheduling. Aspects of architectures such as memory access, shared buses, and memory mapped accelerators will be studied. Assignments will cover various aspects of the design process, starting from implementing and testing specifications, to synthesis and scheduling using high level synthesis tools, and analyzing and improving the resulting architectures.

INTENDED AUDIENCE: Students interested in hardware (VLSI / FPGA) implementations of DSP systems; also useful for those using custom parallel architectures (GPU) PREREQUISITES: Digital Design fundamentals (UG) - Digital Signal Processing (UG) - Processor architecture (UG)

Summary

Course Status :	Completed
Course Type :	Elective
Language for course content :	English
Duration :	12 weeks
Category :	Electrical, Electronics and Communications Engineering
Credit Points :	3
Level :	Postgraduate
Start Date :	29 Jul 2019
End Date :	18 Oct 2019
Exam Date :	16 Nov 2019 IST

Note: This exam date is subject to change based on seat availability. You can check final exam date on your hall ticket.

Page Visits

Course layout

Week 1: Review: Digital systems, DSP, computer architecture Week 2,3: DSP system models; quality metrics and bounds; number representations Week 4,5,6: Implementation: dedicated hardware; transforms; resource sharing; Scheduling: time and resource bounds; allocation, binding, scheduling,techniques Week 7,8,9: Architectures: programmable systems; FSMs and microprograms; instruction extensions; peripheral accelerators Week 10,11: Memory and communication systems: bus structures; DMA; networks-on-chip Week 12: Specialized architectures: Systolic arrays; CORDIC; GPU

Books and references

NIL

Instructor bio

Prof. Nitin Chandrachoodan received his BTech (Electronics and Communication engineering) from IIT Madras in 1996, and PhD from the University of Maryland at College Park in 2002, in the area of high-level synthesis techniques for mapping DSP algorithms to architectures. He has been with the Department of Electrical Engineering at IIT Madras since 2004, where he is currently an Associate Professor. His research interests include digital systems design and design automation tools and techniques, as well as design of embedded systems with a special focus on assistive technologies. He has taught graduate courses on digital integrated circuit design and on mapping algorithms to architectures, and a UG course on data structures and algorithms, as well as a laboratory course on digital design using FPGAs. He is an associate editor of the Springer Journal of Signal Processing Systems.

Course certificate

The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centers.
The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
Date and Time of Exams: 16th November 2019 Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

CRITERIA TO GET A CERTIFICATE

Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course.
Exam score = 75% of the proctored certification exam score out of 100
Final score = Average assignment score + Exam score

YOU WILL BE ELIGIBLE FOR A CERTIFICATE ONLY IF AVERAGE ASSIGNMENT SCORE >=10/25 AND EXAM SCORE >= 30/75.

If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.
Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Madras. It will be e-verifiable at nptel.ac.in/noc.
Only the e-certificate will be made available. Hard copies are being discontinued from July 2019 semester and will not be dispatched.

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