Synthesis of Digital Systems

By Prof. Preeti Ranjan Panda   |   IIT Delhi
This course is about the automatic generation of digital circuits from high-level descriptions. Modern electronic systems are specified in Hardware Description Languages and are converted automatically into digital circuits. We will introduce the VHDL Hardware Description Language, and follow it up with a discussion of the basics of synthesis topics including High-level Synthesis, FSM Synthesis, Retiming, and Logic Synthesis.

INTENDED AUDIENCE: Any Interested Learners
PREREQUISITES:         1. Digital Design (or Logic Design) 2. Data Structuresl

Learners enrolled: 1152


Course Status : Completed
Course Type : Elective
Duration : 12 weeks
Start Date : 29 Jul 2019
End Date : 18 Oct 2019
Exam Date : 17 Nov 2019
Category :
  • Computer Science and Engineering
  • Level : Postgraduate
    This is an AICTE approved FDP course

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    Week 1  :  Course Outline and Introduction to VLSI Design Automation
    Week 2  :  Hardware Description Languages and VHDL
    Week 3  :  Specifying Behaviour and Structure in HDL
    Week 4  :  Introduction to High-level Synthesis
    Week 5  :  Compiler Transformations in High-level Synthesis
    Week 6  :  Scheduling
    Week 7  :  Register Allocation and Timing Issues
    Week 8  :  Finite State Machine Synthesis
    Week 9  :  The Retiming Problem
    Week 10:  Introduction to Logic Synthesis and Binary Decision Diagrams
    Week 11:  Two-level and Multi-level Logic Optimisation
    Week 12:  Technology Mapping and Timing Analysis


     Giovanni de Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill


    Preeti Ranjan Panda received his B. Tech. degree in Computer Science and Engineering from the Indian Institute of Technology Madras and his M. S. and Ph.D. degrees in Information and Computer Science from the University of California at Irvine.
    He is currently a Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Delhi. He has previously worked at Texas Instruments, Bangalore, India, and the Advanced Technology Group at Synopsys Inc., Mountain View, USA, and has been a visiting scholar at Stanford University.

    His research interests are: Embedded Systems Design, CAD/VLSI, Post-silicon Debug/Validation, System Specification and Synthesis, Memory Architectures and Optimisations, Hardware/Software Codesign, and Low Power Design.
    He is the author of two books: Memory issues in Embedded Systems-on-chip: Optimizations and Exploration (Kluwer Academic Publishers) and Power-efficient System Design (Springer). He is a recipient of an IBM Faculty Award and a Department of Science and Technology Young Scientist Award. Research works authored by Prof. Panda and his students have received several honours, including Best Paper nominations at CODES+ISSS, DATE, ASPDAC, and VLSI Design Conference, and Most downloaded paper of ACM TODAES journal.

    Prof. Panda has served on the editorial boards of IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) , ACM Transactions on Design Automation of Electronic Systems (TODAES) , IEEE Embedded Systems Letters and International Journal of Parallel Programming (IJPP), and as Technical Program co- Chair of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) and International Conference on VLSI Design and Embedded Systems (VLSI Design). He has also served on the technical program committees and chaired sessions at several conferences in the areas of Embedded Systems and Design Automation, including DAC, ICCAD, DATE, CODES+ISSS, IPDPS, ASPDAC, and EMSOFT.


    • The course is free to enroll and learn from. But if you want a certificate, you have to register and write the proctored exam conducted by us in person at any of the designated exam centres.
    • The exam is optional for a fee of Rs 1000/- (Rupees one thousand only).
    • Date and Time of Exams: 17 November 2019, Morning session 9am to 12 noon; Afternoon Session 2pm to 5pm.
    • Registration url: Announcements will be made when the registration form is open for registrations.
    • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published. If there are any changes, it will be mentioned then.
    • Please check the form for more details on the cities where the exams will be held, the conditions you agree to when you fill the form etc.

    • Average assignment score = 25% of average of best 8 assignments out of the total 12 assignments given in the course. 
    • Exam score = 75% of the proctored certification exam score out of 100
    • Final score = Average assignment score + Exam score

    • If one of the 2 criteria is not met, you will not get the certificate even if the Final score >= 40/100.
    • Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Madras. It will be e-verifiable at nptel.ac.in/noc.
    • Only the e-certificate will be made available. Hard copies are being discontinued from July 2019 semester and will not be dispatched