Courses » Computer Organization and Architecture A Pedagogical Aspect

Computer Organization and Architecture A Pedagogical Aspect

About the Course:

Computer Organization and Architecture (COA) is a core course in the curricula of Computer Sciences as well as Electronics and Electrical Engineering disciplines at the second-year level in most of the Indian universities and technical institutions. This is the first course in COA and the course would provide students with an understanding of the design of fundamental blocks used for building a computer system and interfacing techniques of these blocks to achieve different configurations of an “entire computer system”.

This course will be developed and taught with respect to Objectives based on Bloom’s Taxonomy. First, we will highlight the main objectives the course is aimed to achieve. Following that, at each module, we will specify the module level objectives and demonstrate how these objectives meet the course level main goals in unison. At the leaf level i.e., the units, we will point the specific objectives of the lecture. Also, it will be demonstrated how the unit level objectives satisfy the parent module level objectives. Further, each module will have a module level problem which needs concepts of all the units therein to solve. Finally, a comprehensive course level problem related to design of “entire computer system” will be discussed which meets all the course level objectives.

Intended Audience: 

UG CSE, Electrical and Electronics Engineering, Electrical Engineering and Information Technology. 

Digital Design.

Industries that will recognize this course:

Processor design industry like Intel, AMD, etc.

4316 students have enrolled already!!

Instructor Details:


Dr. Santosh Biswas is an Associate Professor in the Dept. of CSE IIT Guwahati. He has an experience of 8 years in teaching. His research interests are Fault Tolerance, VLSI Testing, Embedded Systems.

Dr. J K Deka is a Professor in the Dept. of CSE IIT Guwahati. He has an experience of more than 20 years in teaching. His research interests are Formal Modelling and Verification, CAD for VLSI and Embedded Systems (Design, Testing and Verification), Data Mining. 

Dr. Arnab Sarkar is an Asst. Professor in the Dept. of CSE IIT Guwahati. He has an experience of 3 years in teaching and about 2 years in industry. His research interests Real-Time and Embedded Systems, Computer Architecture, Algorithms. 
 Course Layout

Module 1: Basics: Functional Blocks in a Computer System, Number system and Computer Arithmetic (Week 1)

Basic functional blocks of a computer: CPU, memory, input-output subsystems, control unit. Data representation: signed number representation, fixed and floating point representations, character representation. Computer arithmetic - integer addition and subtraction, ripple carry adder, carry look-ahead adder, etc. multiplication - shift-and-add, Booth multiplier, carry save multiplier, etc. Division - restoring and non-restoring techniques, floating point arithmetic.

  1. Unit 1: Building blocks: Digital Logic System, Number Systems and Representation of Information
  2. Unit 2: Computer Arithmetic and ALU
  3. Unit 3: Structural and Functional view of Computer

Module 2: Addressing Modes, Instruction Set and Instruction Execution Flow (Week 2, 3 and 4)

Instruction set architecture of a CPU - registers, instruction execution cycle, RTL interpretation of instructions, addressing modes, instruction set. Case study - instruction sets of a generic CPU.

  1. Unit 1: Component of Central Processing Unit (CPU) and External Interface
  2. Unit 2: Main Memory
  3. Unit 3: Instruction Execution
  4. Unit 4: Instruction Format
  5. Unit 5: Instruction Set
  6. Unit 6: Addressing Modes-1
  7. Unit 7: Addressing Modes-2
  8. Unit 8: Flags and Conditional Instructions
  9. Unit 9: Instruction: Procedure CALL/RETURN

Module 3: Hardware and Micro-program based control Unit Design (Week 5, 6 and 7)

CPU control unit design: hardwired and micro-programmed design approaches, Case study - design of a control unit of a simple hypothetical CPU.

  1. Unit 1: Instruction Cycle and Micro-operations
  2. Unit 2: Control Signals and Timing sequence
  3. Unit 3: Control Signals for Complete
  4. Instruction execution
  5. Unit 4: Handling Different Addressing Modes
  6. Unit 5: Handling Control Transfer Instructions
  7. Unit 6: Design of Hard-wired Controlled Control Unit
  8. Unit 7: Different Internal CPU bus Organization
  9. Unit 8: Micro-instruction and
  10. Micro-program Unit
  11. 9: Organization of Micro-programmed Controlled Control Unit

Module 4: Memory Architecture (Week 8, 9)

Memory system design: semiconductor memory technologies, memory organization: Memory interleaving, concept of hierarchical memory organization, cache memory, cache size vs. block size, mapping functions, replacement algorithms, and write policies.

  1. Unit 1: Binary Cell and Memory Unit
  2. Unit 2: Memory Cell Construction
  3. Unit 3: Memory Unit and Interfacing
  4. Unit 4: Cache Memory
  5. Unit 5: Mapping Functions Unit 6: Replacement Policy

Module 5: Peripherals and Input-Output (Week 10, 11)

Peripheral devices and their characteristics: Input-output subsystems, I/O transfers - program controlled, interrupt driven and DMA

  1. Unit 1: Input-Output Primitives
  2. Unit 2: I/O Instructions and Addressing of I/O devices
  3. Unit 3: Programmed I/O
  4. Unit 4: Interrupt Driven I/O
  5. Unit 5: DMA Transfer Unit 6: Storage Devices

Module 6: Performance Enhancement of Processor (Week 12, 13)

Introduction to concepts focusing on enhancing performance of processors i.e., Advanced Architecture

  1. Unit 1: Performance enhancement: Pipeline
  2. Unit 2: Performance enhancement: Parallelism
  3. Unit 3: Pipeline Strategy
  4. Unit 4: Multi-Processor
  5. Unit 5: Interconnection Networks
  6. Unit 6: Cache Coherence

Suggested Reading:
  1. William Stallings. “Computer organization and architecture: designing for performance”. Pearson Education India, 2000.
  2. Carl Hamacher, Zvonko Vranesic and Safwat Zaky. “Computer Organization”, McGraw Hill, 2011.
  3. David A. Patterson, John L. Hennessy. “Computer organization and design: the hardware/software interface”. Elsevier, 2011.

  • The exam is optional for a fee.
  • Date of Exam: April 28th 2019 (Sunday).
  • Time of Exam: Morning session 9am to 2 noon; Afternoon session: 2pm to 5pm
  • Registration url: Announcements will be made when the registration form is open for registrations.
  • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.

  • Final score will be calculated as : 25% assignment score + 75% final exam score
  • 25% assignment score is calculated as 25% of average of  Best 8 out of 12 assignments
  • E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Guwahati. It will be e-verifiable at nptel.ac.in/noc.