This course will introduce advanced concepts in analog circuit design specifically relevant to CMOS IC design. It will cover circuit noise and mismatch, their analysis, and their impact on CMOS opamp design. As prerequisites, the student is expected to have undergone a course on (a) basic circuit theory and analysis (b) signals and systems and (c) MOS analog circuits. At the end of this course, the student should be able to design and analyze several types of CMOS opamps at the transistor level.
UG course (or equivalent) on: Basic Electrical Circuits, Signals and Systems, Analog Circuits
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Prof. S.Aniruddhanis an assistant professor in the Integrated Circuits and Systems group of the department of Electrical Engineering at Indian Institute of Technology Madras. He works broadly in the area of Analog IC design, with specific focus on RFIC design. He obtained a B. Tech. degree in Electrical Engineering from IIT Madras in 2000, and a Ph.D. degree from the University of Washington, Seattle in 2006. Between 2006 and 2011, he worked in the RF-Analog group at Qualcomm Inc., San Diego, designing integrated circuits for Cellular RF applications.
COURSE LAYOUT Week 1 Introduction to Integrated Circuits; Review of some simple MOS amplifiers Week 2 Noise in circuits; Noise analysis of common circuits Week 3 Mismatch in circuits Week 4 Introduction to negative feedback; frequency response and Bode plots Week 5 Loop gain and stability; Dominant pole compensation Week 6 Block level conceptualization of single- and two-stage opamps Week 7 Differential and common-mode analysis; Differential amplifiers Week 8 Single-stage opamp Week 9 Telescopic opamp Week 10 Folded cascode opamp Week 11 Two-stage opamp Week 12 Fully differential opamps; common-mode feedback
Design of Analog CMOS Integrated Circuits by Behzad Razavi; Tata McGraw-Hill Edition 2006 (ISBN: 0070529035).
The exam is optional for a fee.
Date and Time of Exams: April 28 (Saturday) and April 29 (Sunday) : Morning session 9am to 12 noon;
Exam for this course will be available in one session on both 28 and 29 April.
Registration url: Announcements will be made when the registration form is open for registrations.
The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.
Final score will be calculated as : 25% assignment score + 75% final exam score.
25% assignment score is calculated as 25% of average of best 8 out of12 assignments.
E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup. It will have the logos of NPTEL and IIT MADRAS. It will be e-verifiable at nptel.ac.in/noc
TEACHING ASSISTANTS Theertham Raviteja I'm one of the TAs, assisting Prof.Aniruddhan, for this course. I'm pursuing my masters in IIT Madras. Currently, I'm working on CT Delta Sigma modulators. I would like to help you in any queries on this course. Please feel free to post it on our forum. Hope you'll go through great learning experience from this course! Aditya Narayanan I am a Ph.D. student in IIT Madras working on phase locked loops. I would be glad to help you with any queries. Anantha M S Ashwin Kumar R S I am a Ph.D. student in IIT Madras, and will be assisting this course. Deepthi B
I am a Ph.D. student in IIT Madras working on serial interfaces. I will be helping Prof.Aniruddhan in running this course. Please feel free to drop your queries regarding this course in course forum page. Suraj S Kumar I am an MS student in IIT Madras and I will be assisting this course. Ashik Anuvar
I am an M.Tech student at IITM working on CTDSMs.I will be assisting you in this course.Please feel free to post your queries in the forum. Sankeerth D