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Embedded Systems-- Design Verification and Test


An embedded system (ES) can be described as a computer system, however, unlike a general purpose system, ESs are designed for specific functionalities and are integrated with sensors and actuators. Often ES have real-time computing constraints. Major advantages of ES compared to their general purpose counterparts include low power, low area, low per-unit cost, high operating frequency etc. Most of the modern electronic systems, ranging from a simple elevator controller to a complex avionics control system, are ESs. However, ESs involve integrating hardware-software (i.e., co-design) in a single platform and interfacing sensors-actuators, which make their design a real challenge and a multi-disciplinary problem. The increase in complexity of modern ESs mandates automation in their design. Given a system which we intend to implement, the design process majorly evolves through four distinct but often overlapping and iterative phases:
(i) Modeling: This may be regarded as a systematic specification of the intended system behavior– that is, it tells, what the system should do. Models should mathematically capture both static (system states) and (how state changes occur over time) dynamic properties of the system at a desired level of abstraction, so as to allow systematic analysis.
(ii) Design: Given the model based logical depiction of a system along with estimates on performance and resource requirements of various components, we embark onto the design phase, which derives appropriate structural representations and implementation methodologies,corresponding to the specified behavior – that is, it tells, how a system shall do, what it should do.Design involves consideration of both hardware and software, to take care of different conflicting verticals such as performance, cost, flexibility, energy dissipation etc. An overall system which includes both hardware and software components must consider various issues and apply appropriate mechanisms such that end-to-end performance objectives (like critical real-time constraints) are always satisfied. For example, important issues may include obtaining execution-time estimates of different components and analyzing interferences during their execution, both from – the external environment and other co-executing components. These issues are typically handled using mechanisms such as the use of more predictable artifacts like compiler-controlled memories and employment of appropriate scheduling techniques at various levels. Overviews of all these design strategies will be discussed in this course.
(iii) Verification and Validation: This phase may be considered to be the process of gaining a deeper understanding of a system through dissection – that is, it attempts to answer the question, why a design exhibits a certain characteristic (or fails to do what a model says it should do). Verification and test have been intensively studied and understood for hardware systems and software programs separately. However, ES not only consist of hardware components, a large portion is realized by firmware and programs. There are lots of issues and challenges if verification is to be performed on systems involving hardware software co-designs e.g., different platforms of describing the hardware and software designs, interfaces of hardware-software etc. In this part of course we will discuss verification of ESs and various evolving techniques to handle them.
(iv) Testing basically involves determining if the fabricated system meets the required behavior. This is accomplished by applying physical inputs and matching the outputs with golden signature. Test methodologies and test goals differ in the hardware and software domains. In conventional testing methodologies, software and hardware are tested separately. This divided approach to software and hardware testing does not address the embedded system as a whole. Further, these schemes do not address the complexity that may arise due to integration of software and hardware. In the test module of this course, we will focus on hardware testing, software validation and integration testing. Also focus will be given on testing methodologies that address complex embedded systems like NoC testing, concurrent testing etc.

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Final Exam (in-person, invigilated, currently conducted in India) is mandatory for Certification and has INR Rs. 1100 as exam fee

INTENDED AUDIENCE: UG and PG students of CSE, Electrical and Electronics Engineering, Electrical Engineering


UG/PG: UG and PG

PREREQUISITES: Digital Design and Computer Architecture

INDUSTRY SUPPORT:All Embedded System design/application industries like Intel, Samsung etc. and CAD industries like Cadence, Synopsys, Agilent etc.


Dr. Santosh Biswas is an Associate Professor in the Dept. of CSE IIT Guwahati. He has an experience of 8 years in teaching. His research interests are Fault Tolerance, VLSI Testing, Embedded Systems

Dr. J K Deka is a Professor in the Dept. of CSE IIT Guwahati. He has an experience of more than 20 years in teaching. His research interests are Formal Modelling and Verification, CAD for VLSI and Embedded Systems (Design, Testing and Verification),Data Mining

Dr. Arnab Sarkar is an Asst. Professor in the Dept. of CSE IIT Guwahati. He has an experience of 3 years in teaching and about 2 years in industry. His research interests Real-Time and Embedded Systems, Computer Architecture, Algorithms.


Week 1  :  Introduction and Modeling
Week 2  :   Hardware-Software Co-Design principles and details of hardware design
Week 3  : Introduction to Scheduling in embedded systems
Week 4  :  Scheduling in embedded systems-Advanced issues and Case study 
Week 5  :  Introduction to Formal Verification 
Week 6  :  Verification for Embedded Systems
Week 7  :  Test: Introduction to Digital Testing
Week 8  :  Embedded System hardware Testing
Week 9  :  Advances in Embedded System hardware Testing
Week 10  :  Testing for Embedded Software Systems


1. Peter Marwedel, P. Marwedel,“Embedded System Design”, Springer,2011
2. Wayne Wolf, Components, 2 nd Kaufmann Computers as Edition, Morgan
3. Abhik Roychoudhury, Embedded Systems and Software Validation, 1 st Edition, Morgan Kaufmann
4. M. Huth and M. Ryan, Logic in Computer Science modeling and reasoning about systems, Cambridge University Press, 2nd Edition, 2004
5. Bushnell and Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal Circuits, Kluwer Academic Publishers, 2000
  • The exam is optional for a fee.
  • Date and Time of Exam: October 28 (Sunday)
  • Time of Exams: Morning Session 9 am to 12 pm; Afternoon session: 2pm to 5pm.
  • Exam for this course will be available in both morning & afternoon sessions.
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  • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.
  • Final score will be calculated as : 25% assignment score + 75% final exam score
  • 25% assignment score is calculated as 25% of average of  Best 8 out of 12 assignments
  • E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Guwahati.It will be e-verifiable at nptel.ac.in/noc.