Courses » Multi-Core Computer Architecture – Storage and Interconnects

Multi-Core Computer Architecture – Storage and Interconnects


We are in the era of multi-core systems where even the simplest of handheld devices like a smart phone houses many processors in a single chip. The core counts are ever increasing from 8 to 10 in smart phones to over 100s in super computers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication framework are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in memory-subsystems and interconnects of Tiled Chip Multi-Core Processors with few introductory sessions on advanced superscalar processors. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further.

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All content including discussion forum and assignments, is free

Final Exam (in-person, invigilated, currently conducted in India) is mandatory for Certification and has INR Rs. 1100 as exam fee

Anyone in CSE and related fields (like ECE, EEE, IT etc.) with an interest of exploring Multi-Core Computer Architecture


UG/PG: UG and PG

PREREQUISITES: Final year undergraduates or above in Computer Science and related fields (like ECE, EEE, IT etc.).
A basic understanding of Computer Organisation & Architecture will be added advantage.

INDUSTRY SUPPORT: Intel, AMD, IBM, HP, Apple, Samsung etc.


Dr. John Jose is an Assistant Professor in Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, Assam since July 2015. Prior to this he has over 10 years of teaching experience at both undergraduate and graduate level in AICTE approved NBA/NACC accredited engineering institutes in Kerala. He did his B.Tech degree in CSE from Cochin University, Kerala. He was a rank holder in M.Tech degree from Vellore Institute of Technology (VIT University). He completed his Ph.D degree from Indian Institute of Technology Madras. He is currently supervising 5 Ph.D thesis and 5 M.Tech thesis. His area of interests is in on-chip interconnection networks and cache management techniques for large multicore systems. Recently he has started working on pre-fetching and compression techniques for Tiled Chip Multicore Processors. He is the principal investigator of two sponsored R&D projects funded by DST, Govt of India. He is having active research collaboration with University of Catania-Italy, ITRI Taiwan, and BITS Pilani-Dubai Campus. During his doctoral studies in IIT Madras, he received outstanding teaching assistant award for eight consecutive semesters. He is a reviewer for many national and international peer reviewed journals and member of technical program committee for many IEEE/ACM national and international conferences. He is a resource person to computer architecture related symposia and workshops in many technical institutes all over India. He has given many technical presentations in various international conferences held at Brazil, UAE, Singapore, France, South Korea and United States in the fields of computer design, interconnection networks, and design automation. He has many international IEEE & ACM peer reviewed conference publications and few transactions journal papers to his credit. He is the recipient of ACM-SIGDA, IEEE-CEDA, IARCS & DRDO grants for various research presentations held in various international venues. He is the IIT Guwahati coordinator for Ishan Vikas program of MHRD, Govt. of India. He was the course coordinator and resource persons for MHRD sponsored GIAN course in Scalable On-Chip Interconnects for Many-Core Systems held in May 2017 at IIT Guwahati. He is a resource person for many career guidance seminars/ workshops to various technical institutes and schools. He is a motivational speaker for many companies, schools and engineering institutions. He is an active member of professional societies like ACM, IEEE, ISTE and CSI.


Week 1  :  Fundamentals of instruction pipeline for superscalar processor design
Week 2  :   Memory hierarchy design, cache memory - fundamentals and basic optimisations
Week 3  : Cache memory – advanced optimisations, performance improvement technqiues
Week 4  :  gem5 simulator – build and run, address translations using TLB and page table
Week 5  :  DRAM – organisation, access techniques, scheduling algorithms and signal systems.
Week 6  :  Introduction – Tiled Chip Multicore Processors (TCMP), Network on Chips (NoC)
Week 7  :  NoC router – architecture, design, routing algorithms and flow control techniques.
Week 8  :  Advanced topics in NoC and storage – compression, prefetching, QoS.


1. Computer Architecture - A Quantitative Approach-5e John L. Hennessy, David A. Patterson Morgan Kaufman.
2. Memory System - Cache, DRAM and Disk Bruce Jacob, Spencer W. Ng, David T. Wang Morgan Kaufman.
3. Principles and Practices of Interconnection Networks William J. Dally, Brian P. Towles Elsevier.
  • The exam is optional for a fee.
  • Date and Time of Exam: October 7, 2018 (Sunday)
  • Time of Exams: Morning session 9am to 12 noon; Afternoon session: 2pm to 5pm.
  • Exam for this Course will be available in both morning & afternoon sessions.
  • Registration url: Announcements will be made when the registration form is open for registrations.
  • The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.


  • Final score will be calculated as : 25% assignment score + 75% final exam score
  • 25% assignment score is calculated as 25% of average of  Best 6 out of 8 assignments
  • E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup.It will have the logos of NPTEL and IIT Guwahati. It will be e-verifiable at http://nptel.ac.in/noc/