About the course
Testing is an integral part of the VLSI design cycle. With the
advancement in IC technology, designs are becoming more and more complex,
making their testing challenging. Testing occupies 60-80% time of the design
process. A well structured method for testing needs to be followed to ensure
high yield and proper detection of faulty chips after manufacturing. Design for
testability (DFT) is a matured domain now, and thus needs to be followed by all
the VLSI designers. In this context, the course attempts to expose the students
and practitioners to the most recent, yet fundamental, VLSI test principles and
DFT architectures in an effort to help them design better quality products that
can be reliably manufactured in large quantity.
Digital Design / Digital Logic
Industries that will recognize this course
Companies involved in development of VLSI chips
Santanu Chattopadhyay received his PhD from
Indian Institute of Technology (IIT) Kharagpur in 1996. He is currently a
Professor in the Department of Electronics and Electrical Communication
Engineering, IIT Kharagpur. His research interests include Embedded Systems,
System-on-Chip (SoC) and Network-on-Chip (NoC) Design and Test, Power- and
Thermal-aware Testing of VLSI Circuits and Systems. He has published more than
150 papers in reputed international journals and conferences. He has published
several text and reference books in the related areas. He is a senior member of
IEEE and an editorial board member of IET Circuits Devices and Systems.
Week 1:Introduction: Importance, Challenges, Levels of abstraction, Fault Models, Advanced issues
Week 2:Design for Testability: Introduction, Testability Analysis, DFT Basics, Scan cell design, Scan Architecture
Week 3:Design for Testability: Scan design rules, Scan design flow .
Fault Simulation: Introduction, Simulation models
Week 4:Fault Simulation: Logic simulation, Fault simulation
Week 5:Test Generation: Introduction, Exhaustive testing, Boolean difference, Basic ATPG algorithms
Week 6:Test Generation: ATPG for non stuck-at faults, Other issues in test generation
Built-In-Self-Test: Introduction, BIST design rules
Week 7:Built-In-Self-Test: Test pattern generation, Output response analysis, Logic BIST architectures
Week 8:Test Compression: Introduction, Stimulus compression
Week 9:Test Compression: Stimulus compression, Response compression
Week 10:Memory Testing: Introduction, RAM fault models, RAM test generation
Week 11:Memory Testing: Memory BIST
Power and Thermal Aware Test: Importance, Power models, Low power ATPG
Week 12:Power and Thermal Aware Test: Low power BIST, Thermal aware techniques
• The exam is optional for a fee. Exams will be on 23 April 2017.
• Time: Shift 1: 9am-12 noon; Shift 2: 2pm-5pm
• Any one shift can be chosen to write the exam for a course.
• Registration url: Announcements will be made when the registration form is open for registrations.
• The online registration form has to be filled and the certification exam fee needs to be paid. More details will be made available when the exam registration form is published.
• Final score will be calculated as : 25% assignment score + 75% final exam score.
• 25% assignment score is calculated as 25% of average of 12 weeks course: Best 8 out of 12 assignments.
• E-Certificate will be given to those who register and write the exam and score greater than or equal to 40% final score. Certificate will have your name, photograph and the score in the final exam with the breakup. It will have the logos of NPTEL and IIT KHARAGPUR. It will be e-verifiable at nptel.ac.in/noc.